Path: utzoo!attcan!uunet!willett!ForthNet
From: ForthNet@willett.UUCP (ForthNet articles from GEnie)
Newsgroups: comp.lang.forth
Subject: Forth Engines / Harris
Message-ID: <1037.UUL1.3#5129@willett.UUCP>
Date: 31 May 90 03:35:06 GMT
Organization: Latest link in the ForthNet chain.  (Pgh, PA)
Lines: 21


 Date: 05-28-90 (20:30)              Number: 566 (Echo)
   To: ANIL RODRIX                   Refer#: NONE
 From: JACK WOEHR                      Read: NO
 Subj: HARRIS RTX DESIGN CONTEST     Status: PUBLIC MESSAGE

 >Jack W. thought the external addressing was deactivated, so I'm not sur
 >about that.

        Actually, I said that I thought I had read a line in the
 manual saying that "use of ASIC bus for peripheral I/O was an
 artifact". Now that I have read manual more carefully, believe it
 works. Concat /GIO with GA0,1,2 for address decoding. ASIC data
 bus appears at JP3. Will be testing this week, will post results.

                =jax=

 NET/Mail : RCFB Golden, CO (303) 278-0364 VESTA & Denver FIG for Forth!
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