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From: wendyt@june.cs.washington.edu (Wendy Thrash)
Newsgroups: comp.arch,comp.sys.alliant
Subject: Alliant FX/8 Cache Info Needed
Message-ID: <12104@june.cs.washington.edu>
Date: 1 Jun 90 21:57:12 GMT
Sender: wendyt@cs.washington.edu
Reply-To: wendyt@june.cs.washington.edu (Wendy Thrash)
Organization: U of Washington, Computer Science, Seattle
Lines: 18

In order to finish a paper by the end of this quarter (!), 
I need to get more detailed information on the Alliant FX/8
data cache than I currently have available.  I'd appreciate
mail from anyone who can tell me
1) Most important:  How many bytes are in a cache line/block?
2) What's the difference between their "2-way interleaved"
   cache and a 2-way set associative cache?
3) When there are two cache modules on the system, does each
   service a separate four-CE clump (assuming 8 CE's)?
   What exactly do Alliant mean when they say that adding
   a second module produces a four-way interleaved cache?
4) Is it true that each cache module is 256K = 128K x 2?
   That's what my FX/8 Product Summary says, but Gallivan,
   Jalby, et. al. (1988 IJSCA) describe the FX/8 cache as 128K.

Please note that this is not an attempt to get someone else to
write the paper for me; I need more information about the cache
to explain some anomalous (but pleasing) results I've produced.