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From: kevine@vast.eecs.unsw.oz (Kevin Elphinstone (4th Year))
Newsgroups: comp.sys.amiga
Subject: Re: Bus Speeds doc & question
Message-ID: <724@usage.csd.unsw.oz.au>
Date: 25 May 90 10:23:21 GMT
References: <1843@mindlink.UUCP> <1990May23.021804.12469@uncecs.edu> <11765@cbmvax.commodore.com>
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Reply-To: kevine@vast.eecs.unsw.oz (Kevin Elphinstone)
Organization: VLSI And Systems Technology Laboratory, EECS, UNSW, Australia
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20Mbytes/sec bus speed on an A3000 is not as bad as some of you are making
out it is. I checked the docs I have for MCA on IBM's new toy, the RISC
System 6000, and they claim 20M to 25M sustainable, and up to 40M peak.
But before you're head swells to much, the cache <-> memory speed is
400Mbytes/sec peak. They use a 128 bit bus with two 64 bit memory banks,
with four way interleaving in each bank to give a claimed cycle time of
40nsec.
Pretty amazing stuff.
It seems that for 32 bit buses though, the A3000 stacks up pretty well

Kevin