Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!cbmvax!valentin
From: valentin@cbmvax.commodore.com (Valentin Pepelea)
Newsgroups: comp.sys.amiga.tech
Subject: Re: PowerVisor and floating point coprocessor
Message-ID: <11977@cbmvax.commodore.com>
Date: 30 May 90 19:03:52 GMT
References: <23May1990110844167@BLEKUL11.BITNET> <1420@marlin.NOSC.MIL>
Reply-To: valentin@cbmvax (Valentin Pepelea)
Distribution: comp.sys.amiga.tech
Organization: Commodore, West Chester, PA
Lines: 31

In article <1420@marlin.NOSC.MIL> aburto@marlin.nosc.mil.UUCP
(Alfred A. Aburto) writes:
>
> Please note that the Motorola Programmer's Reference Manual M68000PM/AD 
> dated 1989 has an error in describing the FSAVE instruction format. Page
> 4-17 of that document shows the FSAVE instruction format with bit 8 
> (counting from zero) set to zero, however bit 8 is a 1 for this instruction. 

Well done. Make sure you report this to Motorola.

> Also, a problem I found when checking for the presence or absence of 
> a 68851 MMU co-processor (020 only) is that while I was expecting an
> F-Line exception (vector $2C) for the PFLUSHA instruction on an 020
> without 68851 MMU I received INSTEAD a Co-Processor Protocol exception
> (vector $34).  This happened with an 020/882 board from CSA which had
> no 68851 MMU and it indicated some kind of a hardware problem with
> the Co-Processor interface.

Dave Haynie reported the same problem with the CSA board back when he was
testing his SetCPU program. Try out SetCPU and see what kind of processors
it reports.

The problem seems to be that the CSA board improperly decodes the FCx lines
and assumes that any F-line instruction is a math coprocessor instruction.

Valentin
-- 
The Goddess of democracy? "The tyrants     Name:    Valentin Pepelea
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kill a god."                               UseNet:  cbmvax!valentin@uunet.uu.net
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