Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!rutgers!bpa!cbmvax!valentin
From: valentin@cbmvax.commodore.com (Valentin Pepelea)
Newsgroups: comp.sys.amiga.tech
Subject: Re: MC68881/2 Support (hello, Dave Haynie)
Message-ID: <11996@cbmvax.commodore.com>
Date: 31 May 90 03:54:47 GMT
References: <1181@metaphor.Metaphor.COM>
Reply-To: valentin@cbmvax (Valentin Pepelea)
Organization: Commodore, West Chester, PA
Lines: 30

In article <1181@metaphor.Metaphor.COM> djh@dragon.metaphor.com (Dallas J.
Hodgson) writes:
>
> Since the FFP instructions trap out thru the FLINE vector anyway (if there's
> no coprocessor present) why don't we EMULATE a 6888x when the traps occur?

Too much time would be spent decoding and emulating the coprocessor
instructions. And what if someone plugs in a Weitek math coprocessor? The
math coprocessors execute in 30 cycles what would take 3000 cycles otherwise.
Emulating the instruction in software would take more than that. And what if
the user has merely a 68000? Only the 68010 and higher processors have
instruction suspension-completion mechanisms.

The correct solution is to provide a shared library of math functions, and
that's what we do. Those functions automatically take advantage what ever
hardware the user has, thus the programmer does not have to worry about
the configuration of the platform on which his software is about to run.

The 68040 does not have a floating point coprocessor, nor the coprocessor
interface of the 68020 & 68030. But it implements the most used instructions
in hardware, and lets a software emulate the remaining less used instructions.
The 25MHz 68040 will therefore achieve a superior performance than a 33MHz
68030/68882. Now that makes sense.

Valentin
-- 
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