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From: aburto@marlin.NOSC.MIL (Alfred A. Aburto)
Newsgroups: comp.sys.amiga.tech
Subject: Re: PowerVisor and floating point coprocessor
Message-ID: <1427@marlin.NOSC.MIL>
Date: 31 May 90 19:33:30 GMT
References: <23May1990110844167@BLEKUL11.BITNET> <1420@marlin.NOSC.MIL> <11977@cbmvax.commodore.com>
Reply-To: aburto@marlin.nosc.mil.UUCP (Alfred A. Aburto)
Distribution: comp.sys.amiga.tech
Organization: Naval Ocean Systems Center, San Diego
Lines: 28

In article <11977@cbmvax.commodore.com> valentin@cbmvax (Valentin Pepelea) writes:
>In article <1420@marlin.NOSC.MIL> aburto@marlin.nosc.mil.UUCP
>(Alfred A. Aburto) writes:
>>
>> Please note that the Motorola Programmer's Reference Manual M68000PM/AD 
>> dated 1989 has an error in describing the FSAVE instruction format. Page
>> 4-17 of that document shows the FSAVE instruction format with bit 8 
>> (counting from zero) set to zero, however bit 8 is a 1 for this instruction. 
>
>Well done. Make sure you report this to Motorola.
>

Thanks and yes I'll make sure Motorola is aware of the typo ....

>The problem seems to be that the CSA board improperly decodes the FCx lines
>and assumes that any F-line instruction is a math coprocessor instruction.
>

This explains why then I received the Co-Processor Protocol exception and
not the F-Line exception (which normally one would expect).  It was a very
puzzling problem and it took some fooling around to figure out what was
happening and how to account for it.


Thanks for the feedback.

Al Aburto
aburto@marlin.nosc.mil