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From: toddpw@tybalt.caltech.edu (Todd P. Whitesel)
Newsgroups: comp.sys.apple2
Subject: Re: 16 bit data bus 65816
Message-ID: <1990May30.224509.13034@laguna.ccsf.caltech.edu>
Date: 30 May 90 22:45:09 GMT
References: <210@fawlty.towers.oz>
Sender: news@laguna.ccsf.caltech.edu
Organization: California Institute of Technology, Pasadena
Lines: 43

In article <210@fawlty.towers.oz> johnmac@fawlty.towers.oz (John MacLean) writes:

[ a bunch of stuff I largely agree with, except one thing ]

putting 1 meg fixed on the motherboard makes a lot of sense, considering that
not much else changed. Your argument against it doesn't hold up because the
same thing could be said about the built-in RAM on the ROM 01. I agree that
socketed chips are far safer and that DIPs let you replace them one at a time,
but as memory gets more and more reliable and prices come down ($60 for a 1 meg
SIMM these days) there are fewer reasons to use DIPs, especially because SIMMs
are sturdy little cards rather than a sets of chips which must be individually
installed. The arguments against SIMMs are mostly uninformed paranoia at this
point, IMHO. (I speak as one who was slowly convinced over the last year.)

>Take a good look at the 68000 series and the Macs; ever had the system bomb
>while accessing memory at an odd address; I wonder what the reason for
>this could be. (HINT: count the address and data lines on early 68000s).

Do your homework. The 68000 series was intended from the start to use a word
wide bus; you are supposed to get a bus error if you try to access a word at
an odd address. (BYTE accesses work fine at any address.) This was a conscious
decision on the part of Motorola to avoid the extra memory circuitry. Given
that they were designing the system from scratch, it was a pretty smart thing
to do because then nobody would write code that used odd addresses all over the
place -- on the 8086 the CPU takes a performance hit because it does two bus
accesses for every odd word since you obviously forgot to word align your data
structures in the assembler.

However, the 68020 & up take a similar performance hit from non-long-aligned
long accesses, and do two bus accesses.

>Is Motorola or Apple a big name?

By 'big names' I meant Motorola and Intel, neither of whom have implemented a
scheme with "smart memory" in it (to my knowledge). I figure that they must
have considered the idea but decided against it.

I still feel that if you are going to give the 65816 a wider data bus then a
cache system designed for it will be much more cost-effective than a "smart
memory" system. Caches simply aren't as expensive as they used to be.

Todd Whitesel
toddpw @ tybalt.caltech.edu