Path: utzoo!attcan!uunet!samsung!munnari.oz.au!uhccux!virtue!cantva!phys169
From: PHYS169@canterbury.ac.nz (Mark Aitchison, U of Canty; Physics)
Newsgroups: comp.sys.ibm.pc
Subject: Re: DRAM speed
Message-ID: <7613@canterbury.ac.nz>
Date: 29 May 90 10:32:28 GMT
References: <2660AECB.29143@paris.ics.uci.edu>
Lines: 21

In article <2660AECB.29143@paris.ics.uci.edu>, levine@ics.uci.edu (David Levine) writes:
> I heard that it is not a good idea to use DRAM that is rated much faster
> than required, e.g., 70 ns in place of 120 ns.  Ignoring the price
> difference, is this true?  If so, why?
> 
As I understand it, there are two reasons:

(a) there might be "junk" on the bus for a short time that is not a problem to
the slow memory chips, but could be to fast chips (Chip specs often quote times
when input address & data lines must be stable by, as well as times when output
lines will have stabilised to their correct values). If the board was designed
for slow chips, it *might not* work with significantly faster chips.

(b) faster chips usually consume more power, introduce current pulses on the
power supply lines that are more synchronised (sharper and more severe) - so
the bypass capacitors on the board might not be adequate, and can have
different loading (capacitance and resistance) on the bus which was probably
designed to compensate for standing waves only when certain chips were in
place.

Mark Aitchison.