Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!brunix!tac
From: tac@cs.brown.edu (Theodore A. Camus)
Newsgroups: comp.sys.m68k
Subject: mc68040 I/D coherency
Message-ID: <41463@brunix.UUCP>
Date: 31 May 90 18:38:33 GMT
Sender: news@brunix.UUCP
Reply-To: tac@cs.brown.edu (Theodore A. Camus)
Organization: Brown University Department of Computer Science
Lines: 18


A quick question :

  The mc68040 apparently has separate on-chip instruction and data 
caches (4k each).  I was curious what method they chose to solve the
problem of self-modified code, where the D cache has a copy of a 
modified instruction, but the I cache has an old copy.  

Just curious - 
   - Ted

(p.s. yes I know it is bad practice.  Disallowing it is a valid method,
      just an inflexible one.)

  CSnet:     tac@cs.brown.edu                          Ted Camus  
  ARPAnet:   tac%cs.brown.edu@relay.cs.net             Box 1910 CS Dept
  BITnet:    tac@browncs.BITNET                        Brown University
  "An ounce of example is worth a pound of theory."    Providence, RI 02912