Path: utzoo!attcan!uunet!mcsun!hp4nl!philapd!ssp11!dolf
From: dolf@idca.tds.PHILIPS.nl (Dolf Grunbauer)
Newsgroups: comp.sys.m68k
Subject: Re: mc68040 I/D coherency
Message-ID: <764@ssp11.idca.tds.philips.nl>
Date: 31 May 90 21:30:09 GMT
References: <41463@brunix.UUCP>
Organization: Philips Information Systems, Apeldoorn, The Netherlands
Lines: 14

In article <41463@brunix.UUCP> tac@cs.brown.edu (Theodore A. Camus) writes:
=  The mc68040 apparently has separate on-chip instruction and data 
=caches (4k each).  I was curious what method they chose to solve the
=problem of self-modified code, where the D cache has a copy of a 
=modified instruction, but the I cache has an old copy.  

There is no detection of this situation on the MC68040. You should avoid
it by flushing & disabling the caches and hoping the modified instruction
is not already in the pipeline.
-- 
Dolf Grunbauer      Tel: +31 55 433233 Internet dolf@idca.tds.philips.nl
Philips Information Systems            UUCP     ...!mcsun!philapd!dolf
Dept. BS Software,  P.O. Box 245, 7300 AE Apeldoorn, The Netherlands 
read: error in reading .signature