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From: valentin@cbmvax.commodore.com (Valentin Pepelea)
Newsgroups: comp.sys.m68k
Subject: Re: mc68040 I/D coherency
Message-ID: <12055@cbmvax.commodore.com>
Date: 1 Jun 90 03:08:16 GMT
References: <41463@brunix.UUCP>
Reply-To: valentin@cbmvax (Valentin Pepelea)
Organization: Commodore, West Chester, PA
Lines: 24

In article <41463@brunix.UUCP> tac@cs.brown.edu (Theodore A. Camus) writes:
>
>   The mc68040 apparently has separate on-chip instruction and data 
> caches (4k each).  I was curious what method they chose to solve the
> problem of self-modified code, where the D cache has a copy of a 
> modified instruction, but the I cache has an old copy.  

'They' chose not to support this practice at all. Writing self modifying
code (Ahem - self distructing code) is not just difficult, it's darn well
impossible on most systems.

The only solution I can see for you is to flush the instruction cache for the
particular address in question, and execute a NOP to synchronise the pipeline.

Geez, I can't believe I am telling you how to write bad code! Hopefully I
missed some subtle quirk of the '040 which would make this practice impossible
under any circumstances.

Valentin
-- 
The Goddess of democracy? "The tyrants     Name:    Valentin Pepelea
may distroy a statue,  but they cannot     Phone:   (215) 431-9327
kill a god."                               UseNet:  cbmvax!valentin@uunet.uu.net
             - Ancient Chinese Proverb     Claimer: I not Commodore spokesman be