Path: utzoo!attcan!uunet!lll-winken!sun-barr!ccut!titcca!etlcom!gama!oyanagi
From: oyanagi@gama.is.tsukuba.ac.jp (Yoshio Oyanagi)
Newsgroups: comp.sys.super
Subject: Re: QCDPAX attained 12.25 GFLOPS peak speed.
Message-ID: <5148@gama.is.tsukuba.ac.jp>
Date: 2 Jun 90 06:03:51 GMT
References: <5074@gama.is.tsukuba.ac.jp>
Reply-To: oyanagi@gama.is.tsukuba.JUNET (Yoshio Oyanagi)
Organization: Info Sci & Elec, Univ of Tsukuba, Tsukuba-City, Ibaraki 305, JAPAN
Lines: 39

In article <5074@gama.is.tsukuba.ac.jp> oyanagi@gama.is.tsukuba.JUNET (Yoshio Oyanagi) writes:

>       ===QCDPAX attained 12.25 GFLOPS peak speed===

We received several questions and comments.

>QCDPAX is a parallel computer with 432 PU's (Processing Units).   
>Each PU is running in 28.7 MFLOPS peak speed, and the system in 
>about 12.38 GFLOPS at peak.  12.25 GFLOPS speed is measured for
>the summation of squares of 500,000 elements within each PU.

This is not a "BENCHMARK", but only an Olympic record.  You may be
interested in the Livermore Loop, Linpack benchmark, or Perfect Club
benchmark.  Those are not our targets.  We have constructed QCDPAX
as an engine for lattice QCD simulation.  The QCDPAX is not
a supercomputer in this sense.  


>Each PU is a single board vector processor, and employs 

>	2MB SRAM for vector data store(35ns, Japanese), 
>	4MB DRAM for program and archive data store(100ns, Japanese).  

Some people are interested whose memory chips we used.  We used three
kinds of SRAM chips of Fujitsu, Hitachi and Mitsubishi and DRAM chips
of NEC.


There is one important comment which we have forgotten to mention.

The performance of the machine at University of Columbia made by 
Norman Christ and his collaborators, which is also dedicated to QCD 
simulations, is expected to be similar to our machine's, although we 
don't have at hand the data of their performance to compare with. 
 
					QCDPAX Collaboration
						Y. Oyanagi
						Y. Iwasaki
						T. Shirakawa