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From: jc@atcmp.nl (Jan Christiaan van Winkel)
Newsgroups: comp.arch
Subject: Re: Randomised Instruction Set Computer
Message-ID: <613@atcmpe.atcmp.nl>
Date: 4 Jun 90 18:52:10 GMT
References: <3131@goanna.cs.rmit.oz.au>
Organization: AT Computing, Nijmegen, The Netherlands
Lines: 15

From article <3131@goanna.cs.rmit.oz.au>, by ok@goanna.cs.rmit.oz.au (Richard A. O'Keefe):
> Suppose you had a RISC machine with, say, 64 genuine instructions encoded
> in a 7 bit field, the remaining 64 being mapped to "illegal opcode" and
> that the machine had an on-chip memory of 128x7 bits, so that instruction
> decoding went through this memory?  Suppose that there were a system call

I believe that there were special versions of the Z80 processor that used a
different instruction set, i.e. all opcodes were encrypted using a normal
substitution cipher. This means that normal roms for the boot process 
could not be used, and that every copy of the CPU could have a different 
opcode set.
JC
-- 
Jan Christiaan van Winkel              Tel: +31 80 566880     jc@atcmp.nl
AT Computing       P.O. Box 1428       6501 BK Nijmegen       The Netherlands