Path: utzoo!attcan!uunet!mstan!amull
From: amull@Morgan.COM (Andrew P. Mullhaupt)
Newsgroups: comp.arch
Subject: Direct Mapped Caches
Keywords: Collision Avoidance
Message-ID: <1020@s6.Morgan.COM>
Date: 4 Jun 90 16:53:07 GMT
Organization: Morgan Stanley & Co. NY, NY
Lines: 11

We have an application which carefully arranges for data to begin on
the same low order address bits. When we run this application on 
machines with direct mapped caches, we get more collisions than we
would otherwise expect.

We are considering simple solutions, like randomly offsetting the
low order bits by the size of a cache line when allocating data,
but I'd like to know if other solutions are to be preferred.

Thanks in advance,
Andrew Mullhaupt