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From: ins425v@monu4.cc.monash.edu.au (mr  t.h. mackenzie)
Newsgroups: comp.sys.amiga.tech
Subject: 1MEG Chip & A501 on REV6 A500
Message-ID: <2400@monu1.cc.monash.oz>
Date: 1 Jun 90 07:55:15 GMT
Sender: news@monu1.cc.monash.oz
Organization: Monash University, Clayton, Vic 3168, Australia
Lines: 35

Perhaps this has been discussed earlier but I have only just been given
access to the news network.

Does anyone know how to get an Amiga 500 with a Rev 6 board running with 
1MEG chip ram AS WELL AS the A501 memory expansion. The second 1/5 Meg of the
chip ram (when it is installed) runs off the same _RAS1 line as the A501.

I currently have a circuit to split the _RAS1 line (Combining the A19 and A23
lines into A19 of Obese Angus so it responds to both) using the _RAS1 line,
the _RAS0 line (to detect refresh for the A501 which only has 41256 rams), the
_RAMEN line from Gary to decide whether Angus or the processor is initiating the
access, (I have also tried using _BLIT for this), and A19 , A23 to decide on
which set of ram.

So far I have (with circuit Rev3) succeeded in letting the processor have
access to both sets of ram, but when angus tries to access the ram on it's 
own behalf the machine crashes. (Evidently the RAS1 is delayed too long by 
the extra decoder circuitry so that the ram does not have the required 15ns
between _RAS and _CAS) My current decoder has a delay time of approximately
8 ns using Fast TTL. The circuit MAY work if this can be decreased to 4ns
(This may be possible with Fast TTL open collector OR gates, but I cannot get
these!)

The Circuit:
A19(Obese Angus) = A19 + A23
_Refresh = _RAS1 + _RAS0
_UpperChip = _BLIT + _RAS1  OR !_RAMEN + _RAS1 (I have tried both)

_ChipRAS1= _Refresh._UpperChip.(_RAS1 + !A19)
_FastRAS1 = _Refresh.(_RAS1 + !A23)
These last 2 signals are passed to the appropriate ram bank via the 74F244 
already on board. (It has 2 spare lines)

Note that this is working. (I have a software fix to convert 0x80000..0x100000
to fast ram so Angus doesn't do anything to it.)