Path: utzoo!utgpu!news-server.csri.toronto.edu!mailrus!uunet!comp.vuw.ac.nz!dsiramd!actrix!geoff
From: geoff@actrix.co.nz (Geoff McCaughan)
Newsgroups: comp.sys.amiga.tech
Subject: Re: 1MEG Chip & A501 on REV6 A500
Message-ID: <1990Jun5.220006.8095@actrix.co.nz>
Date: 5 Jun 90 22:00:06 GMT
References: <2400@monu1.cc.monash.oz>
Organization: Actrix Public Access UNIX, Wellington, New Zealand
Lines: 33

In article <2400@monu1.cc.monash.oz> ins425v@monu4.cc.monash.edu.au (mr  t.h. mackenzie) writes:
>Does anyone know how to get an Amiga 500 with a Rev 6 board running with 
>1MEG chip ram AS WELL AS the A501 memory expansion. The second 1/5 Meg of the
>chip ram (when it is installed) runs off the same _RAS1 line as the A501.
>
>The Circuit:
>A19(Obese Angus) = A19 + A23
>_Refresh = _RAS1 + _RAS0
OK, you got this bit right!!
>_ChipRAS1= _Refresh._UpperChip.(_RAS1 + !A19)
>_FastRAS1 = _Refresh.(_RAS1 + !A23)

OK, here's how I did it:
NAND _BLIT and A23, pass this to the D input of a D type flipflop. Clock
the flipflop with _CDAC. AND the Q output of the flipflop with _RAS1 for
_RAS1FAST and AND _Q with _RAS1 for _RAS1CHIP (as these are active low
signals, AND them with OR gates). Now OR the resulting signals with
_REFRESH (using AND gates natch).

The you can achieve the same logic with just the NAND gate and an
inverter but it doesn't work, the secret is using _CDAC and the flipflop
which ensures we never change state during a _RAS cycle.

I have been using this hack for a couple of months now and can't break
it. I have also done it to a Rev 5 board (by piggybacking the RAM in the
A501).

I have written up instructions for this hack along with a circuit
diagram for out local Amiga newsletter, so if you want a copy, let me
know your snail address. I guess if there's enough interest I could post
it on the net [ if I can figure out how to do that 8-) ]

Cheers!