Path: utzoo!attcan!uunet!mailrus!cs.utexas.edu!usc!petunia!news
From: rbannon@mira.acs.calpoly.edu (Roy Bannon)
Newsgroups: comp.sys.apple2
Subject: Re: Zip GS
Message-ID: <266b0cc9.61c8@petunia.CalPoly.EDU>
Date: 5 Jun 90 01:37:13 GMT
References: <2995@crash.cts.com>
Reply-To: rbannon@mira.acs.calpoly.edu.UUCP (Roy Bannon)
Organization: Cal Poly State University -- San Luis Obispo
Lines: 29



In article <2995@crash.cts.com> lbotez@pro-sol.cts.com (Lynda Botez) writes:
>Here's some interesting new information about the above-mentioned new product
>from Zip that I gleaned off of a rather well-informed Apple II BBS that I
>frequent....
>
>*********
>
>I went to the Orange Apple Commputer Club meeting today and the President of
>Zip Technology made a presentation demo of the alpha Zip GS board running at
>6.25 Mhz speed.  The key to the new accelerator was a ASIC chip which
>eliminate

>So Zip are the ones who signed the agreement with ASIC.  Not Applied
>Engineering.
>
>Anyone have an update on the ASIC chip and how it's progressing?
>
>Lynda

Actually, I think ASIC in this context means application specific integrated
circuit.  They mention that it reduces the chip count which is consistent with
a custom logic chip.  I don't think a new uP manufacturer would do that to a
very large extent.  I don't know anything new on the progresion of the ASIC
65816.  Hope this makes it a little clearer.

Roy