Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!usc!rutgers!att!watmath!watserv1!watcgl!jvkelley
From: jvkelley@watcgl.waterloo.edu (Jeff Kelley)
Newsgroups: comp.sys.next
Subject: Bus Interface Chip Specs
Keywords: hardware
Message-ID: <1990Jun4.211238.17852@watcgl.waterloo.edu>
Date: 4 Jun 90 21:12:38 GMT
Distribution: comp
Organization: Computer Graphics Laboratory, University of Waterloo, Ontario, Canada
Lines: 14

I'm interested in the multiprocessing support provided by the
NeXT bus interface chip.  Does it have a location monitor
(i.e. source processor writes to a location on target processor
and raises an interrupt on the target processor), a hardware
FIFO (similar to location monitor but data is captured from
the bus during the write cycle and stored in a FIFO queue
for later extraction by the target processor, typically information
like the number of the source processor is sent), or other
support for multiple processors?  (If it has a FIFO, how deep
and how wide?)

--
Jeff Kelley    National Research Council of Canada, Ottawa
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