Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!mcsun!hp4nl!charon!dik
From: dik@cwi.nl (Dik T. Winter)
Newsgroups: comp.arch
Subject: Re: i860 registers/chip in general
Message-ID: <1635@charon.cwi.nl>
Date: 11 Jun 90 23:26:02 GMT
References: <495@tau.megatek.uucp> <8744@brazos.Rice.edu>
Sender: news@cwi.nl
Organization: CWI, Amsterdam
Lines: 23

In article <8744@brazos.Rice.edu> preston@titan.rice.edu (Preston Briggs) writes:
 > How do seperate sets slow your code?  I can think of integer multiplies
 > and perhaps the pipelined loads which can only be done in the FP set.

One important point (that Sun has forgotten to take account of in the SPARC):
it is important to have one of two (perhaps more I cannot think of now)
properties:
a.  A direct datapath from the general registers to the floating point
    registers.
b.  A calling sequence that allows passing parameters in floating point
    registers.
And also important:
c.  Conversion from integer to floating point vice-versa should go from
    integer registers to floating point registers, and the other way around.

The SPARC architecture as defined provides neither a, nor b, nor c, which
results in a considerable slow-down on many floating-point applications.

(Not that want to bash the SPARC, it is a good architecture in quite a
few ways, but it has its architectural defects.)
--
dik t. winter, cwi, amsterdam, nederland
dik@cwi.nl