Path: utzoo!utgpu!news-server.csri.toronto.edu!rutgers!usc!zaphod.mps.ohio-state.edu!mips!synoptics!unix!morgan
From: morgan@unix.SRI.COM (Morgan Kaufmann)
Newsgroups: comp.arch
Subject: Re: Hennessey(sp?)/Patterson book on architecture
Keywords: Who publishes it?
Message-ID: <13033@unix.SRI.COM>
Date: 11 Jun 90 22:27:02 GMT
References: <840@peyote.cactus.org>
Reply-To: morgan@unix.UUCP (Morgan Kaufmann)
Organization: SRI International, Menlo Park, CA
Lines: 62

In article <840@peyote.cactus.org> woan@peyote.cactus.org (Ronald S. Woan) writes:
>I know that someone posted this in the past few weeks, but I tried
>grep'ing through our /usr/spool/news directories to no avail, so it
>must have already expired here. Could someone post the complete
>publishers information on the new architecture book by Hennesey(sp?)
>and Patterson. I believe it is titled "Computer Architecture, A Quantitative
>Approach" and was released in February.
>

Reposting:


COMPUTER ARCHITECTURE:  A QUANTITATIVE APPROACH, by John Hennessy
(Stanford) and Dave Patterson (UC Berkeley).


This book is now available through technical bookstores, and should be
in-stock at the larger stores in major cities.  It can also be ordered
directly from the publisher:

Morgan Kaufmann Publishers,
2929 Campus Drive, Ste 260,
San Mateo, CA 94403,
Tel 415/965-4081. 
VISA, Mastercard, personal checks and money orders will be accepted.
The cost of the title is $54.95 plus $3.50 shipping/handling for
each copy ordered.



Contents: 

1. Fundamentals of Computer Design.
2. Performance & Cost. 
3. Instruction Set Design:  Alternatives and Principles.
4. Instruction Set Examples and Measurements of Use.
5. Basic Processor Implementation Techniques.
6. Pipelining.
7. Vector Processors.
8. Memory Hierarchy Design.
9. Input/Output.
10. Future Directions & Parallel Computation.
Appendices: 
A) Computer Arithmetic, by David Goldberg (Xerox PARC)
B) Complete Instruction Set Tables (VAX, 360, 8086)
C) Detailed Instruction Set Measurements (VAX, 360, 8086, DLX)
D) Time Versus Frequency Measurements
   (VAX 11/780, IBM 370/168, 8086 in an IBM PC, DLX)
E) Survey of RISC Architectures
   (DLX, i860, MIPS, M88000, SPARC).

Another title of interest that expands upon performance issues for
cache and memeory hierarchies is due to be published May 27th, also
from Morgan Kaufmann:

CACHE & MEMORY HIERARCHY DESIGN:  A PERFORMANCE DIRECTED APPROACH,
by Steven A. Przybylski (MIPS), $33.95
Contents:  Intro.  Background Material.  The Cache Design Problem
and its Solution.  Performance)Directed Cache Design.  Multi-Level
Cache Hierarchies.  Summary, Implications and Conclusions. 
Appendices:  A) Validation of Empirical Results, B) Modeling Write
Strategy Effects.