Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uwm.edu!bionet!agate!shelby!cis!raje From: raje@dolores.Stanford.EDU (Prasad Raje) Newsgroups: comp.arch Subject: Re: 1st 64 Megabit DRAM Message-ID: Date: 12 Jun 90 18:12:04 GMT References: <16348@smunews.UUCP> <1990Jun11.032747.15462@agate.berkeley.edu> <511@dg.dg.com> <57316@bbn.BBN.COM> Sender: news@cis.Stanford.EDU (USENET News System) Organization: Center for Integrated Systems, Stanford Lines: 34 In-reply-to: khoult@bbn.com's message of 12 Jun 90 13:58:02 GMT About the 64Mbit DRAM: I havent read any of the trade rag announcements so I dont know if Hitachi made a separate announcement, but I was there at the VLSI Circuits Symposium in Hawaii where a paper on a 64Mb DRAM was presented. Here is the reference: Y.Nakagome et al, "A 1.5V Circuit Technology for 64Mb DRAMs", VLSI Circuits Symposium Digest, p 17, 1990. The paper mainly concentrated on circuit techniques (sense amp, word line driver, half Vcc voltage generator) for 1.5 V operation that will be required for 64Mbit DRAMs. They did have a chip microphotograph of the 64M DRAM but did not present measured data on this RAM. The access time of 50ns was obtained by circuit simulation. They probably do have working circuits for their new sense amps etc and did show some scope traces of wordline, and data out waveforms. Some details on the technology for those who do not have access to the reference (most libraries may not have the Digest yet) Organization: 16Mx4 Techonology: 0.3um P substrate, triple well CMOS Oxide thickness: 65A Gate Length: 0.5um (N), 0.6um (P) Cell: Stacked Capacitor cell, 44fF Ccell 0.8 um x 1.6 um = 1.28 um^2 Chip size: 9.74 mm x 20.28 mm = 197.5 mm^2 Power Supply: 1.5 or 3.3V external, 1.5V internal Access time: 50ns Enjoy Prasad