Path: utzoo!utgpu!news-server.csri.toronto.edu!ois.db.toronto.edu!jonah
Newsgroups: comp.arch
From: jonah@db.toronto.edu (Jeff Lee)
Subject: Re: 1st 64 Megabit DRAM
Message-ID: <90Jun12.183151edt.2787@ois.db.toronto.edu>
Organization: University of Toronto, CSRI
References: <16348@smunews.UUCP> <1990Jun11.032747.15462@agate.berkeley.edu> <511@dg.dg.com> <57316@bbn.BBN.COM> <RAJE.90Jun12111204@dolores.Stanford.EDU> <31499@ut-emx.UUCP>
Date: 12 Jun 90 22:33:00 GMT
Lines: 18

hcobb@walt.cc.utexas.edu (Henry J. Cobb) writes:

>	Just give me a port with 21 bits of address and 32 bits of
>data for direct connection to my CPU.  If I need more than 8MB of RAM,
>I'll probably need more than one processor anyway.

A 20MHz processor plus a dedicated 8MB 50ns memory (i.e. no cache) --
or a board full of these -- would seem to be quite useful for some
applications.  On the other hand, a 4-bit wide memory means you need
64MB (8 chips) to get a 32-bit wide memory and 128MB (16 chips) to make
a 64-bit wide memory -- which is more than you may want dedicate as
"local" memory for a smart controller of some sort.

Can anyone with a hardware design background say what the problem is
with wider memory chips (BESIDES having to change the packaging/pinout
of the memory chips).

j.