Path: utzoo!attcan!uunet!cs.utexas.edu!usc!orion.oac.uci.edu!uci-ics!megatek!rstewart
From: rstewart@megatek.UUCP (Rich Stewart)
Newsgroups: comp.arch
Subject: i860 registers, follow up
Message-ID: <501@tau.megatek.uucp>
Date: 12 Jun 90 21:15:10 GMT
Organization: Megatek Corporation, San Diego, Ca.
Lines: 16

I guess I should add a bit more info to my previous posting.
I am interested in the chip from the point of view of
the best software perfomance I can get in critical routines.
I still have not found a compiler that does a good job of this so,
this is why I feel separating the register sets leads to slower
software:

On the i860 you have to do an integer to float register move in order
to do an integer multiply, and then you have to move it back to do
any other integer ops on the result. (Integer multiplies take place in
the fpu)

Also the floating point stores and loads can work on 64 bit aligned
words in the same amount of time as 32 bits, but you have got to
move all of those integer results back into the floating point registers
to take advantage of this.