Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!rutgers!mephisto!udel!sbcs!ameristar!rick From: rick@ameristar (Rick Spanbauer) Newsgroups: comp.arch Subject: Re: 1st 64 Megabit DRAM Message-ID: <1990Jun13.051630.6829@ameristar> Date: 13 Jun 90 05:16:30 GMT References: <57316@bbn.BBN.COM> <31499@ut-emx.UUCP> Organization: Ameristar Technology, Inc Lines: 25 In article <31499@ut-emx.UUCP> hcobb@walt.cc.utexas.edu (Henry J. Cobb) writes: > The mistakes of the present carried to the technology of the future. > Eight MegaBytes stacked behind a 50ns nibble-wide port is >almost a second for a blind burst read. > A 24-bit wide "full color" bitplane built from these suckers >only gives a 500x800 display at 50Hz. (thou you could have 40 such >screens packed in the chips). > Just give me a port with 21 bits of address and 32 bits of >data for direct connection to my CPU. If I need more than 8MB of RAM, >I'll probably need more than one processor anyway. > > Henry J. Cobb hcobb@ccwf.cc.utexas.edu Well said. There is light at the end of the tunnel though. It seems many/most of the majors are looking to widen their memory ports, eg some have 64kx16 rams on the horizon, x8 vrams now, etc. TI is starting a line of ssop packaged x16 buffer/register parts. Now all we need is a packaging technology to contain all those 128+ bit busses, eg multichip modules anyone? ;-) Of course a 32 bit port into vram isn't going to make you a happy camper either if you want your hdtv resolution (1920x1080) screen to update at a reasonable rate. Me? I want at least 256 bits into my frame buffer.. Rick Spanbauer Ameristar