Path: utzoo!attcan!uunet!mcsun!unido!gmdzi!thg
From: thg@gmdzi.UUCP (Thomas Hagemann)
Newsgroups: comp.arch
Subject: Re: 1st 64 Megabit DRAM
Message-ID: <2527@gmdzi.UUCP>
Date: 12 Jun 90 16:06:04 GMT
References: <511@dg.dg.com>
Organization: GMD, Sankt Augustin, F. R. Germany
Lines: 24

From article <511@dg.dg.com>, by lewine@dg.dg.com (Don Lewine):
> Here is the information that I have:
> 	Hitachi announced the development of a 64M bit DRAM [[Did not say 
> 							      anything about
> 							      working parts.]]
> 	Operates on a single 1.5V power supply
> 	Access time is 50 ns.
> 	Power dissipation is 44mW.
> 	The device uses 0.3 micron technology
> 	Chips size is 9.74 x 20.28 mm.
> 	Memory cells are constructed with multi-layer capacitors.
> 	Hitachi expects to use this DRAM in protable OA equipment, note book
> 		size PC.
> 
> 		(source: DENPA SHINBUN 6/8/90)
in addition, HITACHI plans to ship samples in 3 to 4 years, mass production
will start in 1995.
At the same time, MITSUBISHI ELECTRIC said it developed a new architecture
for 64 MB DRAM-Chips with 40 ns access time, which is also applicable for
next generation 256 MB DRAM's.
-- 
Thomas Hagemann, German National Research Center for Computer Science (GMD)
                 Schloss Birlinghoven, 5205 St. Augustin 1, West Germany
                 thg@gmdzi.gmd.de                      ++49-2241-14-2079