Path: utzoo!attcan!uunet!samsung!usc!apple!agate!shelby!portia.stanford.edu!dhinds From: dhinds@portia.Stanford.EDU (David Hinds) Newsgroups: comp.arch Subject: Re: 1st 64 Megabit DRAM Message-ID: <1990Jun13.051957.17219@portia.Stanford.EDU> Date: 13 Jun 90 05:19:57 GMT References: <57316@bbn.BBN.COM> <31499@ut-emx.UUCP> Organization: AIR, Stanford Universit Lines: 31 In article <31499@ut-emx.UUCP> hcobb@walt.cc.utexas.edu (Henry J. Cobb) writes: > > The mistakes of the present carried to the technology of the future. > Eight MegaBytes stacked behind a 50ns nibble-wide port is >almost a second for a blind burst read. > A 24-bit wide "full color" bitplane built from these suckers >only gives a 500x800 display at 50Hz. (thou you could have 40 such >screens packed in the chips). Gee, I guess that progress in the semiconducter industry isn't always defined by who can make the biggest, fastest, most colorful frame buffer. > Just give me a port with 21 bits of address and 32 bits of >data for direct connection to my CPU. If I need more than 8MB of RAM, >I'll probably need more than one processor anyway. One would assume that the intended market for this device is not "[your] CPU" :-) There seem to be a number of single-processor systems around that CAN make reasonable use of more than 8MB of memory. It isn't clear to me why DRAM's are nearly always bit-wide or nibble- wide, besides tradition. Compatibility doesn't seem to be an issue for this chip. Is it possible that error correction circuitry can somehow be more efficient this way? I would expect that this chip has a significant amount of space devoted to error correction. Alternatively, (more likely?) the intention is to keep the markets for successive generations of chips from overlapping too much. To move up to the next higher density, you are forced to buy a lot more memory this way. -David Hinds dhinds@popserver.stanford.edu