Path: utzoo!attcan!uunet!mailrus!iuvax!noose.ecn.purdue.edu!en.ecn.purdue.edu!wailes
From: wailes@ecn.purdue.edu (Tom S Wailes)
Newsgroups: comp.arch
Subject: Re: On Chip Emulator
Summary: Instruction Fetch Override
Message-ID: <1990Jun13.152910.22061@ecn.purdue.edu>
Date: 13 Jun 90 15:29:10 GMT
References: <9598@pt.cs.cmu.edu>
Organization: Purdue University Engineering Computer Network
Lines: 31

In article <9598@pt.cs.cmu.edu>, lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) writes:
> 
> There's a nifty new wrinkle in the new Motorola DSP, the 96002.
> 
> It contains what Motorola refers to as an on-chip emulator. The
> "OnCE" has its own dedicated serial interface, and accepts commands
> to set breakpoints, report on internal values, and so on.

> 
[ stuff deletede ]
> 

> It might be interesting to discuss what else it should do: perhaps
> keep the last few branch-from addresses, which I believe the National
> '16 did.
> 
> -- 
> Don		D.C.Lindsay 	leaving CMU .. make me an offer!

     Does any present microprocessor allow the instruction  fetch to be 
disabled?  For instance, imagine a multiprocessor machine made of many
microcomputers that could be switched from normal mode to SIMD mode by
defeating the normal instruction fetch and allowing the direct placement
of the instruction word on the address lines.  This would allow a very
quick MIMD to SIMD switch of processor computation.  Thus an algorithm
that was best modeled using both MIMD and SIMD modes (in different areas
of the code) could be switched effectively.  Has any present microprocessor
maker allowed such a "test mode?"

                                           Tom Wailes
                                           wailes@en.ecn.purdue.edu