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From: huck@aspen.IAG.HP.COM (Jerry Huck)
Newsgroups: comp.arch
Subject: Synchronization primitives and cache coherence
Message-ID: <1360003@aspen.IAG.HP.COM>
Date: 12 Jun 90 18:58:16 GMT
Organization: HP Information Architecture Group - Cupertino, CA
Lines: 22

I'm trying to catalog the synchronization approaches that current commercial
architectures are using between processors and I/O modules.  Could others
send me (or post) information on architectures they are aware of?  I'll be
happy to tabulate and summarize.  The questions are:
  1.) Which instruction level synchronization primitives are supported?
  2.) How are I/O modules accesses synchronized with processor caches?

For example, PA-RISC defines the "load and clear" instruction as an
atomic memory-based synchronization primitive (its just like test and
set except it clears the location).  Cache coherence with I/O modules
requires Software support to flush the memory addresses at the appropriate
times.

For those curious 'why?', I'm looking into the current standards
activity in cache coherent buses (like futurebus+ and SCI) and their
requirements on future processors.  These efforts define both coherence
protocols and synchronization primitives (but that would be a different
note).

Thanks,
Jerry Huck (Hewlett Packard)
           (huck@iag.hp.com)