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From: tim@proton.amd.com (Tim Olson)
Newsgroups: comp.arch
Subject: Re: On Chip Emulator
Message-ID: <1990Jun13.193821.3895@mozart.amd.com>
Date: 13 Jun 90 19:38:21 GMT
References: <9598@pt.cs.cmu.edu> <1990Jun13.152910.22061@ecn.purdue.edu>
Sender: usenet@mozart.amd.com (Usenet News)
Reply-To: tim@amd.com (Tim Olson)
Organization: Advanced Micro Devices, Inc., Austin, Texas
Lines: 26

In article <1990Jun13.152910.22061@ecn.purdue.edu> wailes@ecn.purdue.edu (Tom S Wailes) writes:
|      Does any present microprocessor allow the instruction  fetch to be 
| disabled?  For instance, imagine a multiprocessor machine made of many
| microcomputers that could be switched from normal mode to SIMD mode by
| defeating the normal instruction fetch and allowing the direct placement
| of the instruction word on the address lines.  This would allow a very
| quick MIMD to SIMD switch of processor computation.  Thus an algorithm
| that was best modeled using both MIMD and SIMD modes (in different areas
| of the code) could be switched effectively.  Has any present microprocessor
| maker allowed such a "test mode?"

The Am29000 has an asynchronous control interface that is normally
used by hardware emulators and debuggers; it controls transitions
between RUN, HALT, SINGLE-STEP, and LDTESTIR modes.  The later mode
latches whatever is presented on the instruction bus into the
Instruction Decode latch, allowing the emulator or debugger to "jam"
its own instruction stream into the processor to save/restore state
and interface with the rest of the system.

It is conceivable that this mode could be used as you suggest, but it
wouldn't run full speed, since transitions between LDTESTIR and
SINGLE-STEP modes would have to be made for each instruction.

	-- Tim Olson
	Advanced Micro Devices
	(tim@amd.com)