Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!dino!ux1.cso.uiuc.edu!ux1.cso.uiuc.edu!aglew From: aglew@lasso.csg.uiuc.edu (Andy Glew) Newsgroups: comp.arch Subject: Re: Synchronization primitives and cache coherence Message-ID: Date: 13 Jun 90 21:38:15 GMT References: <1360003@aspen.IAG.HP.COM> Sender: usenet@ux1.cso.uiuc.edu (News) Organization: University of Illinois, Computer Systems Group Lines: 10 In-Reply-To: huck@aspen.IAG.HP.COM's message of 12 Jun 90 18:58:16 GMT I just noticed that Jerry is specifically interested in synchronization between processor and I/O modules, whereas my survey was between processor and memory (and other processors). Although it should apply to memory mapped I/O. Nonetheless, I hope that some people may be interested in the comparative tables of survey primitives I have posted. -- Andy Glew, aglew@uiuc.edu