Path: utzoo!attcan!uunet!mcsun!ukc!inmos!braa!davidb From: davidb@braa.inmos.co.uk (David Boreham) Newsgroups: comp.arch Subject: Re: 1st 64 Megabit DRAM Message-ID: <7502@ganymede.inmos.co.uk> Date: 14 Jun 90 11:09:41 GMT References: <16348@smunews.UUCP> <1990Jun11.032747.15462@agate.berkeley.edu> <511@dg.dg.com> <57316@bbn.BBN.COM> <31499@ut-emx.UUCP> <90Jun12.183151edt.2787@ois.db.toronto.edu> Sender: news@inmos.co.uk Reply-To: davidb@inmos.co.uk (David Boreham) Organization: none Lines: 23 In article <90Jun12.183151edt.2787@ois.db.toronto.edu> jonah@db.toronto.edu (Jeff Lee) writes: > >A 20MHz processor plus a dedicated 8MB 50ns memory (i.e. no cache) -- >or a board full of these -- would seem to be quite useful for some >applications. On the other hand, a 4-bit wide memory means you need Hmm, by the time these little beauties hit the market 20MHz will be almost DC :) and probably only used for very low power applications. 50ns is about adequate on today's fast CMOS processors. >Can anyone with a hardware design background say what the problem is >with wider memory chips (BESIDES having to change the packaging/pinout >of the memory chips). Packaging and pinout is no problem. Finding the power to drive all the output pins fast is a bit of a problem. However, don't expect 64Mbit DRAMs to hit the market looking anything like today's 1/4Mbit parts. If they do then we really will be in trouble. David Boreham, INMOS Limited | mail(uk): davidb@inmos.co.uk or ukc!inmos!davidb Bristol, England | (us): uunet!inmos.com!davidb +44 454 616616 ex 547 | Internet: davidb@inmos.com