Path: utzoo!attcan!uunet!bywater!arnor!SUHLER@IBM.COM
From: suhler@ibm.com (Paul Suhler)
Newsgroups: comp.arch
Subject: 1st 64 Megabit DRAM
Message-ID: <1990Jun14.145615.24483@arnor.uucp>
Date: 14 Jun 90 14:56:15 GMT
Sender: news@arnor.uucp (NNTP News Poster)
Reply-To: SUHLER@IBM.COM
Organization: IBM Watson Research Center
Lines: 12

David Hinds (dhinds@popserver.stanford.edu) writes:
>     It isn't clear to me why DRAM's are nearly always bit-wide or nibble-
>wide, besides tradition.  Compatibility doesn't seem to be an issue for
>this chip.  Is it possible that error correction circuitry can somehow
>be more efficient this way?  [...]
  
The reason to prefer bit-wide RAMs is that if a single chip fails, then
ECC can still correct the error.  If two or more bits go at once, then
it can't.

Paul Suhler
Hybrid Dataflow Systems