Path: utzoo!utgpu!news-server.csri.toronto.edu!rutgers!usc!zaphod.mps.ohio-state.edu!mips!sgi!rpw3@rigden.wpd.sgi.com From: rpw3@rigden.wpd.sgi.com (Rob Warnock) Newsgroups: comp.arch Subject: Re: Mercury delay lines Message-ID: <62309@sgi.sgi.com> Date: 15 Jun 90 03:34:34 GMT References: <3040@softway.oz> <2694@wrgate.WR.TEK.COM> <1990Jun7.210822.5230@esegue.segue.boston.ma.us> <2701@wrgate.WR.TEK.COM> <10814@medusa.cs.purdue.edu> Sender: rpw3@rigden.wpd.sgi.com Reply-To: rpw3@sgi.com (Rob Warnock) Organization: Silicon Graphics, Inc., Mountain View, CA Lines: 55 In article <10814@medusa.cs.purdue.edu> sxr@babbage.cs.purdue.edu (Saul Rosen) writes: +--------------- | The Mercury Delay Line is not of real current interest in the | world of computer architecture, and there is not much point to | including a technical description here... +--------------- Well, not in and of itself. However, delay-line storage may be about to make a comeback, but instead of sound waves in mercury using light waves in air (or glass or vacuum). At least one of the research projects [e.g., at Bell Labs, per Alan Huang, several years ago at a public seminar] investigating possible all-optical computers has come up with a scheme in which the state of the "micro-engine" is stored as on and off spots in a planar wavefront of light which sweeps through the machine. Each pass through the logic block [literally a block of glass and other stuff!] corresponds to one "clock" of the micro-engine, and all of the logic gates of the micro-engine operate in parallel as the pattern of light sweeps by. Since they anticipate the switching time of the opto components to (eventually, based on device physics) be much less than the propagation time of the "wavefront" around the loop (which includes a regenerator stage), the idea has come up of stacking several micro-engine states one after another, thus making a "barrel processor" out of the beast. With a round-trip time of (say) 5ns and a switching time of 10 ps (including guard bands), you could stack 500 parallel CPUs in the same space as one. Each machine would have a 5 ns micro-cycle time. [Actually, as I recall, they were talking about switching times in the femtoseconds, not picoseconds...] By the way, current optics are good enough to handle a "wavefront" with say 100 x 100 "bits", or 1250 bytes of micro-state. Refined optics could probably handle 1k x 1k bits (?). [Can anybody who knows better comment...???] And of course, your cache memories could be additional "delay lines" which could store more bits in a longer and longer loops, until you get to speeds that could match conventional memories. And you could get a synchronous ring network connecting the various parallel "CPUs" by sending a small portion of the state "wave" through a *slightly* longer path (say, put a tad thicker glass on that portion of one of the mirrors), such that whatever bits were output by a given micro-engine during one microcycle would show up in the next engibe "back" on the next microcycle. [Hmmm... and by shaving off a few microns of glass off another area of the mirror, you could feed some bits *forward*. Counter-rotating rings!] So even though mercury delay lines are dead, delay lines may not be... -Rob ----- Rob Warnock, MS-9U/510 rpw3@sgi.com rpw3@pei.com Silicon Graphics, Inc. (415)335-1673 Protocol Engines, Inc. 2011 N. Shoreline Blvd. Mountain View, CA 94039-7311