Path: utzoo!utgpu!news-server.csri.toronto.edu!mailrus!cs.utexas.edu!sun-barr!newstop!sun!eng.sun.com From: david@eng.sun.com (2. Is it hard on you when you fail?) Newsgroups: comp.arch Subject: Re: Processor architecture to support functional languages Message-ID: <137422@sun.Eng.Sun.COM> Date: 16 Jun 90 05:31:43 GMT References: <5439@midway.cs.glasgow.ac.uk> <90Jun15.211837edt.2773@ois.db.toronto.edu> Sender: david@sun.Eng.Sun.COM Lines: 15 In article <90Jun15.211837edt.2773@ois.db.toronto.edu> jonah@db.toronto.edu (Jeff Lee) writes: >2) 4KB is a fairly reasonable page size. There was a time when 4KB was >considered a *large* page size; of course opinions have changed. >However, 4KB is the smallest page size that completely maps 4GB (32-bit >addresses) in two levels of page map tables with 32-bit PMT entries. I >believe that Sun adopted 8KB pages so they could cover 16MB (the >physical address range of the 68000) in a single level PMT. Then of >course they were stuck with it. The Sun 4/20, 4/60, and 4/65 (aka SLC, SS1, SS1+) have a 4KB page size. The SPARC Reference MMU spec also calls for 4KB pages. -- David DiGiacomo, Sun Microsystems, Mt. View, CA david@eng.sun.com