Path: utzoo!utgpu!news-server.csri.toronto.edu!mailrus!uunet!tut.cis.ohio-state.edu!pt.cs.cmu.edu!MATHOM.GANDALF.CS.CMU.EDU!lindsay From: lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) Newsgroups: comp.arch Subject: Re: 1st 64 Megabit DRAM Message-ID: <9639@pt.cs.cmu.edu> Date: 17 Jun 90 02:19:03 GMT References: <57316@bbn.BBN.COM> <31499@ut-emx.UUCP> <1990Jun13.051630.6829@ameristar> Organization: Carnegie-Mellon University, CS/RI Lines: 49 In article <1990Jun13.051630.6829@ameristar> rick@ameristar (Rick Spanbauer) writes: >Now all we need is a >packaging technology to contain all those 128+ bit busses, eg multichip >modules anyone? ;-) Of course a 32 bit port into vram isn't going to >make you a happy camper either if you want your hdtv resolution (1920x1080) >screen to update at a reasonable rate. Me? I want at least 256 bits into >my frame buffer.. As I've said before in this forum, I see at least nine candidate technologies that will allow cm^2 chips to have 1,000+ pins. (The nine are: 1) flip chip 2) insetting to planarize with substrate 3) multilayer TAB 4) mechanically stacked active regions 5) metallizing a beveled chip edge 6) trenched cantilevers 7) chip vias 8) wafer scale 9) [speculative!] onchip optical elements. If anyone has more [not the Cray-3 technology], I'd appreciate mail. ) Most of these imply or require that you are communicating with something nearby, and in a very controlled environment. Even then, power is going to be an issue, with multilayer TAB probably being the worst. Such a superchip will initially be expensive, just as 40-pin DIPs were once expensive. (The 68000, in its 64 pin DIP, was awesome.) So, the superchip will probably hold a CPU or four, with the pins for primary cache(s) <===> secondary cache. It won't necessarily be a single 1024-signal bus: it may be several buses, and they may be double railed, or unidirectional, or both. Note that clock rates should be past 100 MHz ( ie 10 ns ) by then: it is the agonized search for nanoseconds will drive us to this packaging. The MIPS RC6280 (R6000 ECL box) has an 8 word primary-I-line and a 2 word primary-D-line, i.e. a logical width of 320 bits. That seems consistent with the superchip. The "Micro 2000" suggested by Intel in the Oct89 IEEE Spectrum is described as 250 MHz, one square inch, and with a 2 MB onchip secondary cache. That would have room for 2K+ pins, again consistent with the 32 word (1024 bit) line size of the RC6280 secondary cache. As for frame buffers ... Sony has a 2K x 2K color monitor: 72 Hz is a standard: that gives a pixel rate of 302 MHz, or 24 bits every 3.3 nano. Assuming VRAM with 50 MHz shift rates (twice what MegaScan uses), the refresh alone has to be 144 bits wide. I presume that the non-serial VRAM port needs a similar bandwidth? -- Don D.C.Lindsay leaving CMU .. make me an offer!