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From: janick@bnr.ca (Janick Bergeron 1617964)
Newsgroups: comp.lsi,comp.lsi.cad,comp.std.misc,comp.std.internat
Subject: Question about netlist description in EDIF 200
Message-ID: <1336@bcrka298.UUCP>
Date: 13 Jun 90 20:46:46 GMT
Sender: janick@bnr.ca
Reply-To: janick@bnr.ca
Followup-To: comp.lsi
Lines: 87


The following questions apply to gate-level netlists described
in EDIF 200, not schematics.
The schematics shown here are for illustration purposes only. 


1- Can two nets be connected to the same port of the same
   instance of a cell ??


        Net N -----\       +-----------------
                    \      |
                     \     |       Instance
                      o----| A
                     /     |         "I"
                    /      |
        Net M -----/       +-----------------


     (Net N
       (Joined
         (PortRef A (InstanceRef I))
         ...
       )
     )

     (Net M
       (Joined
         (PortRef A (InstanceRef I))
         ...
       )
     )

         Is this acceptable EDIF 200 ? or should ripper cells
         be used ?


2- In "Using EDIF 200 For Schematic Transfer" published by the EIA,
   two ripper cells are used when a net must be split in two other nets.
   Is this a recommendation of a committee or can a single ripper cell
   be used ?

		       +-----------+
		   +--o|           |o--+
		   |   |  RIPPER   |   +---- Signal(0:1)
                   +--o|	   |o--+
   Signal(0:3) -+--+   |	   |
		|  +--o|	   |o--
		|  |   |   CELL    |
		|  +--o|	   |o--
		|      +-----------+
		|
		|
		|      +-----------+
		|  +--o|           |o--
		|  |   |  RIPPER   |
                |  +--o|	   |o--
                +--+   |	   |
        	   +--o|	   |o------- Signal(2)
        	   |   |   CELL    |
        	   +--o|	   |o--
		       +-----------+


               As described in the EIA publication


		       +-----------+
		   +--o|           |o--+
		   |   |  RIPPER   |   +---- Signal(0:1)
                   +--o|	   |o--+
   Signal(0:3) ----+   |	   |
		   +--o|	   |o------- Signal(2)
		   |   |   CELL    |
		   +--o|	   |o--
		       +-----------+


                Can it be replaced by this ??


Thanks you for your help,
-- 
Janick Bergeron     Bell-Northern Research, Ltd       Ph.: (613) 763-5457
VHDL Tools            P.O. Box 3511, Station C        Fax: (613) 763-2661
                  Ottawa, Ontario, Canada, K1Y 4H7  Flame: 1-800-DEV-NULL
janick@bnr.ca                     library disclaimer; use disclaimer.all;