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From: SLSW2@cc.usu.edu (Roger Ivie)
Newsgroups: comp.sys.dec
Subject: Re: "RISCy VAX" ??
Message-ID: <26139@cc.usu.edu>
Date: 12 Jun 90 15:52:32 GMT
References: <1990Jun11.172604.22994@hayes.fai.alaska.edu>
Lines: 29

In article <1990Jun11.172604.22994@hayes.fai.alaska.edu>, fnddr@acad3.fai.alaska.edu writes:
> While this statement seems plausible for the VAX architectures I've been using
> the last several years, I presume they mean "...can be executed in one cycle."
> Since executing all instructions in one cycle is a (the?) definition of RISC,
> perhaps this is what they have in mind for a RISC-y VAX...getting more of the
> instruction set to execute in a single cycle.

Actually, there's another interpretation. Recall that even now MicroVAXes
don't execute the complete instruction set; the CRC instruction, for instance,
is emulated by software. The hardware simply provides hardware assist to
emulation routines to execute these instructions.

A RISCy VAX could imply even more emulation done by software. The core machine
would execute some small subset of the instruction set (perhaps those that
can reasonably be done in one cycle) and the remaining instructions would
be interpreted.

Just think! It would be capable of executing the entire VAX instruction
set (by helping to interpret what it can't run) AND it would execute those
instructions that it actually runs in a single cycle! Wouldn't that be
fun for the marketing people to build literature around?
-- 
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Roger Ivie

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