Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!tut.cis.ohio-state.edu!rutgers!bpa!cbmvax!bryce
From: bryce@cbmvax.commodore.com (Bryce Nesbitt)
Newsgroups: comp.sys.m68k
Subject: Re: mc68040 I/D coherency
Message-ID: <12565@cbmvax.commodore.com>
Date: 12 Jun 90 01:21:28 GMT
Reply-To: bryce@cbmvax (Bryce Nesbitt)
Organization: Commodore, West Chester, PA
Lines: 24

In article <12558@cbmvax.commodore.com> daveh@cbmvax (Dave Haynie) writes:
>That's not self-modifying code.  The code, as loaded, is of course data-space
>information.  The loader performs the modifications, and then at some point
>this data-space magically is converted to instruction-space.  The only thing
>such a transform can affect is a copyback data cache.  

Except, of course, if the area in question was used for instructions previously
(back to the standard I->D->I problem, though down to a one-in-a-zillion case).
The I cache needs to be accounted for as part of the load operation, part of
relocation, or otherwise.  DMA/Bus snooping would help here, since (it seems)
a snoop affects both I and D caches.

The 68040 manual is a bit vauge on certain snooping and serialization issues.
One can infer that a snoop affects both caches, but one must take on faith that
when section 8 talks about "non-cacheable I/O" it really means "cache inhibited,
nonserialized".  A number of subtle points are not covered, like what happens
for a non-aligned access to a serialized page.


-- 
|\_/|  . "ACK!, NAK!, EOT!, SOH!"  "Lawyers: America's untapped export market."
{X o} .     Bryce Nesbitt, Commodore-Amiga, Inc.
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