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From: amos@taux01.nsc.com (Amos Shapir)
Newsgroups: comp.arch
Subject: Re: Paging page tables
Message-ID: <4137@taux01.nsc.com>
Date: 28 Jun 90 14:39:30 GMT
References: <3300142@m.cs.uiuc.edu>
Organization: National Semiconductor (IC) Ltd, Israel, Home of the Series 32000
Lines: 22
X-Hdate: 5 Tamuz 5750

In article <3300142@m.cs.uiuc.edu> march@m.cs.uiuc.edu writes:
>
>While reading Hennessey and Patterson (p. 437), they mention the fact
>that page tables entries are often paged themselves (with the operative
>word being often).  Now to me, paging you're means of address translation 
>makes no sense.  As they continue to point out, the cost of this is 
>appreciable because one has to swap the PTEs back in and then do the 
>translation.  Given this, just how "often" is this used?

A simple calculation: 32-bit addresses cover 4GB; when using pages
of 4KB (which are rather large as paging systems go) you have
to keep 1M PTE's, which occupy 4MB.  The need to page these is
of course proportional to the amount of virtual memory used vs. the
amount of physical memory that can be tied down in PTE's.

So "often" means - as often as more than a few MB of virtual space
are used.

-- 
	Amos Shapir		amos@taux01.nsc.com, amos@nsc.nsc.com
National Semiconductor (Israel) P.O.B. 3007, Herzlia 46104, Israel
Tel. +972 52 522408  TWX: 33691, fax: +972-52-558322 GEO: 34 48 E / 32 10 N