Path: utzoo!attcan!uunet!aplcen!uakari.primate.wisc.edu!uflorida!mephisto!rutgers!bellcore!messy!mo From: mo@messy.bellcore.com (Michael O'Dell) Newsgroups: comp.arch Subject: Re: Instruction caches and closures Message-ID: <24891@bellcore.bellcore.com> Date: 2 Jul 90 16:40:03 GMT References: <771.267e5501@waikato.ac.nz> <39466@mips.mips.COM> <90Jun19.064421edt.2802@ois.db.toronto.edu> <1694@kunivv1.sci.kun.nl> Sender: news@bellcore.bellcore.com Reply-To: mo@messy.UUCP (Michael O'Dell) Organization: Center for Chaotic Repeatabilty Lines: 14 The SPARCitecture provides for a FLUSH instruction specifically required to be issued by a program when it diddles instructions. (Earlier versions of the SPARCitecture document called it "IFLUSH", but it probably must diddle both caches if there are two, and the single cache if there is only one, so they changed the name at some point.) At Prisma, the first program we found which didn't issue them was the dynamic linker! When we first tried to run a dynolink pgm on the Prisma P1 simulator (with 2 caches), the results were spectacular. The bug was trivial to fix and everyone was appropriately chagrined. -Mike