Path: utzoo!attcan!uunet!mcsun!hp4nl!charon!jack From: jack@cwi.nl (Jack Jansen) Newsgroups: comp.arch Subject: Re: Instruction caches and closures Message-ID: <1756@charon.cwi.nl> Date: 2 Jul 90 21:33:45 GMT References: <1694@kunivv1.sci.kun.nl> <24891@bellcore.bellcore.com> Sender: news@cwi.nl Organization: AMOEBA project, CWI, Amsterdam Lines: 18 This I/D cache discussion sparked a thought: I get the impression that separate I/D caches are used mainly to get the benefit of two-way set associative caches without the cost involved. If there aren't any other added advantages, why not just have two caches that cache both instructions and data, and steal the top address bit to denote which cache to use? The OS can easily set things up so that text segments are mapped in with the top bit clear, and data segments with the top bit set. You could even extend the scheme to add more caches, and let kernel-I references use a different cache from user-I refs, so that the poor application program whose inner loop happens to collide with the clock interrupt routine doesn't suffer unduly. And, of course, this neatly solves the closure problem. -- -- Een volk dat voor tirannen zwicht | Oral: Jack Jansen zal meer dan lijf en goed verliezen | Internet: jack@cwi.nl dan dooft het licht | Uucp: hp4nl!cwi.nl!jack