Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!dg!lewine
From: lewine@dg.dg.com (Don Lewine)
Newsgroups: comp.arch
Subject: Re: Paging page tables
Message-ID: <590@dg.dg.com>
Date: 3 Jul 90 16:16:23 GMT
References: <3300142@m.cs.uiuc.edu>
Reply-To: uunet!dg!lewine (Don Lewine)
Organization: Data General, Westboro, MA.
Lines: 24

In article <3300142@m.cs.uiuc.edu> march@m.cs.uiuc.edu writes:
>
>While reading Hennessey and Patterson (p. 437), they mention the fact
>that page tables entries are often paged themselves (with the operative
>word being often).  Now to me, paging you're means of address translation 
>makes no sense.  As they continue to point out, the cost of this is 
>appreciable because one has to swap the PTEs back in and then do the 
>translation.  Given this, just how "often" is this used?  

First, read ahead through page 445 to understan VAX memory management.  Pay
close attention to Figure 8.27.  The key concept is that user (P0 & P1)
page tables are kept in system space.  System space is paged.

When I was working on the MicroVAX architecture in 1982-83, it seemed that
we could save some gates by making all page tables physical.  This was done
one other computer architectures.  We did some experiments to determine how
often page tables were paged.  I have forgotten the exact numbers, but the
answer was "a great deal."  In fact, the amount of page table paging was high
enough to convince us that we needed to implement full-VAX memory management.

We assumed that VMS could be made smarter and do less paging of page tables,
however, even at that the cost of keeping all page tables in memory was way
to high.  That is, even if VMS only had to read the page tables for the 
current process, there would be a great deal of wasted memory.