Path: utzoo!utgpu!news-server.csri.toronto.edu!clyde.concordia.ca!uunet!bcstec!iftccu!bressler
From: bressler@iftccu.ca.boeing.com (Rick Bressler)
Newsgroups: comp.sys.ibm.pc
Subject: Re: QEMM 5.0 Slo-o-o-o-ws system DMA
Message-ID: <1470013@iftccu.ca.boeing.com>
Date: 27 Jun 90 23:39:14 GMT
References: <3863@trantor.harris-atd.com>
Organization: Boeing Commercial Airplane Group
Lines: 54

Actually, if not useing the mapping features, QEMM has an auto mode that 
will switch out of protected mode when not actually using expanded memory. 
(at least according to the manual).

It seems that there might be enough interest to reprint (by permission)
a note from John Lefor, University of Rochester, Dept of E. Engineering
The following states more clearly than I could some of the issues.

--------------------------------------------------------------------------

When QEMM (or any other '386 EMM) goes into V86 mode various things
have to happen.  First why do they go into V86 mode?  The answer is 
that in order to provide memory at addresses outside of where
real memory exists QEMM must map memory.  In order to map memory the
'386 must be in protected mode or V86 mode (actually V86 mode runs
in protected mode but the task is labelled a V86 task).

Now in V86 mode you have all the overhead of protected mode 
(most instructions take loner to execute since they have to
be checked for protection exceptions).  In addition there is a need
to trap (at least) all interrupt calls and all DMA activity.

The interrupts are trapped and examined.  The trap happen in
protected mode and then the interrupt must be handed down to
the V86 task.  The interrupts must be trapped because in protected
mode interrupts are processed by the IDT while in real mode the
interrupts are processed by interrupt vectors in low memory.

Now DMA --  Becase memory is being mapped all memory move
operations on the CPU have their address translated by a set
of page translation tables.  Unfortunately DMA operations do not
have their addresses processed by these tables so all DMA 
operations must be trapped and the source/destination and
addresses must be examined.  If the memory being moved
is not physically at the same address as the program thinks it
is (because the memory is mapped) then the DMA trap must
translate the addresses to reflect the mapped address.  If the
length of an operation causes the DMA operation to span more
than on contiguous bit of mapped memory then not only must the
I/O address be changed but it must be broken into several 
pieces to allow the translated addresses to correspond to
where it should be placed.

Note that there are even bigger problems with bus master
devices and I/O to translated memory.  To address this 
IBM has announed another specification to let developers
of bus master cards build drivers which can have their
addresses translated by programs that map memory.

I hope this helps you understand the whys of 386 EMMs and
their performance problems.  The magnitude of the impact
on performance will be in part based on the silicon design of
the chip and in part based on the methods chosen by the
EMM writer on how to deal with these problems.