Newsgroups: sci.electronics
Path: utzoo!henry
From: henry@utzoo.uucp (Henry Spencer)
Subject: Re: Frame Buffers
Message-ID: <1990Jun26.154640.26941@utzoo.uucp>
Organization: U of Toronto Zoology
References: <2229@mindlink.UUCP>
Date: Tue, 26 Jun 90 15:46:40 GMT

In article <2229@mindlink.UUCP> a575@mindlink.UUCP (Michael G. Henders) writes:
>...  BUT, how does it work with the more common x1 RAM chips??
>In this case, you access 8 chips in parallel, but you only get one pixel out of
>it, so the access interval is 14 ns; pretty quick for SRAM, and right out for
>DRAM.
>
> I guess one could bank-interleave, but, using 1 Mb chips, this means you end
>up with N times the amount of RAM you actually need, where N is the interleave
>factor; I can't see anyone actually doing this. Clearly, I'm missing something
>fundamental here; can someone tell me what it is??  Thanks much...

The fundamental point is that nobody builds such frame buffers with x1 RAMs.
You have discovered a basic fact:  frame buffers for high-resolution screens
with many bits per pixel need LOTS AND LOTS of bandwidth.  That demands, in
practice, parallelism:  many bits coming out of the memory on each access.
32 or 64 is much more typical than 8.

That pushes designers very strongly towards RAMs with multi-bit outputs,
unless the architecture needs lots of extra memory anyway.  In particular
it very strongly encourages the use of video RAMs, which have both multi-
bit output and a dual-porting scheme which gives *very* wide parallelism
on the time-consuming access to the actual memory array.  Nobody in his
right mind uses anything but VRAMs for frame buffers unless there is some
compelling reason why they won't work for the particular application.
-- 
As a user I'll take speed over|     Henry Spencer at U of Toronto Zoology
features any day. -A.Tanenbaum| uunet!attcan!utzoo!henry henry@zoo.toronto.edu