Path: utzoo!utgpu!news-server.csri.toronto.edu!mailrus!uunet!mcsun!hp4nl!charon!jack
From: jack@cwi.nl (Jack Jansen)
Newsgroups: comp.arch
Subject: Re: Instruction caches and closures
Message-ID: <1782@charon.cwi.nl>
Date: 5 Jul 90 18:52:21 GMT
References: <24891@bellcore.bellcore.com> <1756@charon.cwi.nl> <39868@mips.mips.COM>
Sender: news@cwi.nl
Organization: AMOEBA project, CWI, Amsterdam
Lines: 20

In article <39868@mips.mips.COM> mash@mips.COM (John Mashey) writes:
>In article <1756@charon.cwi.nl> jack@cwi.nl (Jack Jansen) writes:
>>This I/D cache discussion sparked a thought: I get the impression that
>>separate I/D caches are used mainly to get the benefit of two-way
>>set associative caches without the cost involved. If there aren't any
>>other added advantages,...
>
>No, the main reason is to double the peak bandwidth from cache -> CPU
>with the same speed SRAMs.

Ok, but that doesn't invalidate the point: separate I/D caches limit
the OS in the ways it can make best use of the available cache, while
a cache system that uses an address bit (or more address bits) to select
the cache (or cache bank, more correctly) should give the same performance
and more freedom.
--
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