Path: utzoo!utgpu!news-server.csri.toronto.edu!mailrus!uwm.edu!zaphod.mps.ohio-state.edu!usc!snorkelwacker!spdcc!esegue!johnl
From: johnl@esegue.segue.boston.ma.us (John R. Levine)
Newsgroups: comp.arch
Subject: Re: Paging page tables
Message-ID: <1990Jul06.003628.2633@esegue.segue.boston.ma.us>
Date: 6 Jul 90 00:36:28 GMT
References: <3300142@m.cs.uiuc.edu> <1990Jun29.154940.22762@tera.com> <2936@skye.ed.ac.uk>
Reply-To: johnl@esegue.segue.boston.ma.us (John R. Levine)
Organization: Segue Software, Cambridge MA
Lines: 18

I don't get what this argument is about.  Every machine I've ever seen that
has regular (as opposed to inverted) page tables pages the page tables.
Some, like the Vax, do it explicitly by embedding the page table in another
pagable address space.  Most others, such as the IBM 370 and the Intel 386,
get exactly the same effect with two-level page tables.  In both cases, the
page table is broken up into chunks (which always seem to have a size of one
page) and each chunk can be marked resident or non-resident independently.

Except for machines like the PDP-11/70 which has a tiny virtual address
space, the page table is too big to lock down into memory.  Even if you have
the memory, having to allocate a large contiguous chunk of physical memory
is painful, so paged page tables allow scattered allocation of page tables
just like any other memory.

-- 
John R. Levine, Segue Software, POB 349, Cambridge MA 02238, +1 617 864 9650
johnl@esegue.segue.boston.ma.us, {ima|lotus|spdcc}!esegue!johnl
Marlon Brando and Doris Day were born on the same day.