Path: utzoo!utgpu!news-server.csri.toronto.edu!eecg.toronto.edu!distef
Newsgroups: comp.dsp
From: distef@eecg.toronto.edu (Eugenia Distefano)
Subject: questions on DSP32C
Message-ID: <1990Jul12.171144.23305@jarvis.csri.toronto.edu>
Organization: EECG, University of Toronto
Date: 12 Jul 90 21:11:44 GMT
Lines: 9

When the DSP32C is trying to access its on-chip RAM, does the
address appear on the external bus?

If an external interrupt is asserted during the first cycle of 
an external memory access, is that access going to be completed 
before the ISR is invoked?

Thanks,
  -- eugenia