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From: rubinoff@linc.cis.upenn.edu (Robert Rubinoff)
Newsgroups: comp.sys.mac.system
Subject: Re: RAM Chip Speed?
Message-ID: <26729@netnews.upenn.edu>
Date: 5 Jul 90 15:55:17 GMT
References: <1990Jul3.072826.1@mel.cipl.uiowa> <42654@apple.Apple.COM>
Sender: news@netnews.upenn.edu
Reply-To: rubinoff@linc.cis.upenn.edu (Robert Rubinoff)
Organization: University of Pennsylvania
Lines: 29

In article <42654@apple.Apple.COM> austing@Apple.COM (Glenn L. Austin) writes:
>wolf@mel.cipl.uiowa writes:
>[...]  However, the only restriction
>is that all SIMMs within a bank (2/bank on Plus & SE, 4/bank on II-class, &
>SE/30) are the same speed.


NO! NO! NO! NO! NO!

I'm really getting tired of seeing this wrong information repeated over and
over again!

If you think about it, you'd realize that this can't possibly be true!  The
speed rating on a chip is only the guaranteed worst speed the chip will
display.  A chip rated at 150ns might actually respond within 120ns, or 100ns,
or 117.5ns, or any other speed <=150ns.  Thus there is no possible way to get
SIMMS that are "the same speed".

This mistake is presumably a misunderstanding or misremembering of the correct
restriction that all SIMMS within a bank must be the same *size*.  There is
also a restriction on all Macs other than the IIci that if the two banks have
different size SIMMS, the larger ones must go in the first bank.  (I think
the "first" bank is always the one labeled Bank A, but I'm not sure.)

I don't mean to criticize Glenn; he's probably just repeating what he was told.
But I've seen this misinformation dozens of times, and I'm just getting tired
of it.

   Robert