Path: utzoo!attcan!uunet!cs.utexas.edu!know!zaphod.mps.ohio-state.edu!ncar!boulder!gore!jacob
From: jacob@gore.com (Jacob Gore)
Newsgroups: comp.sys.next
Subject: Re: RISC Coprocessor Boards
Message-ID: <130084@gore.com>
Date: 9 Jul 90 18:45:17 GMT
References: <112780@linus.mitre.org>
Reply-To: jacob@gore.com (Jacob Gore)
Organization: Gore Enterprises
Lines: 21

/ comp.sys.next / mek4_ltd@uhura.cc.rochester.edu (Mark Kern) / Jul  9, 1990 /
> 	For example, people have told me that you cannot compare a RISC
> to CISC by comparing MIPS, because of the difference in the two
> architectures. Thus, some people I know are prone to saying CISC will
> give you such and such Real Mips, while RISC will give you RISC Mips. The
> end result is that a RISC chip may have blindingly great MIP stats, but
> actually be no faster than a CISC chip rated at half that.

"1 MIPS" now generally means "the speed of a VAX-11/780".  They run
various benchmarks on the CPU to be rated, then divide the resulting speed
by the speed of that same benchmark on a 780.  This is less meaningless
than just comparing instructions/second of each chip (unless the chips have
the same instruction set).

Of course, one still needs to see if how well the benchmarks correspond to
the use one will put the machine to, and the CPU speed is just one of the
factors that determine the speed of the machine.

Jacob
--
Jacob Gore		Jacob@Gore.Com			boulder!gore!jacob