Path: utzoo!attcan!uunet!tut.cis.ohio-state.edu!cs.utexas.edu!wuarchive!usc!snorkelwacker!bloom-beacon!eru!luth!sunic!tut!funic!santra!cs.hut.fi!jem From: jem@cs.hut.fi (Johan Myreen) Newsgroups: sci.electronics Subject: Re: Frame Buffers Message-ID: Date: 30 Jun 90 18:48:59 GMT References: <2229@mindlink.UUCP> <1990Jun26.154640.26941@utzoo.uucp> <1990Jun26.200549.792@amd.com> Sender: news@santra.uucp (Cnews - USENET news system) Organization: Helsinki University of Technology, Finland Lines: 20 In-Reply-To: phil@pepsi.amd.com's message of 26 Jun 90 20:05:49 GMT In article <1990Jun26.200549.792@amd.com> phil@pepsi.amd.com (Phil Ngai) writes: >I wouldn't be quite so strong about that. VRAMs are a lot more expensive >than regular DRAMs, and since you can run 50 ns page mode cycles on >ordinary DRAMs, you can easily get 20 Mhz * 32 = 640 million bits/sec >or 80 million 8-bit pixels/sec out of 1 megabyte of memory (8 x 256K x 4). >That's 1.3 million pixels/frame at 60 Hz. Aren't you a little optimistic in saying that you can easily get a bandwidth of 20 MHz * 32 out of regular DRAMs? You will have to write to the chips too, which, in addition to making one cycle unavailable for a read operation, also makes the next read 'out of page'. The calculations should be made for the worst case, not the best case. And even a realistic assumption of 1.3 million pixels per frame doesn't give you a very big margin, if you want a display of say 1024 pixels across. -- Johan Myreen jem@cs.hut.fi